package mult 

import chisel3._
import chisel3.util._

class RegInitNext(val bits: Int) extends Module {

  val io = IO(new Bundle{
    val load = Input(Bool())
    val init = Input(UInt(bits.W))
    val out  = Output(UInt(bits.W))
  })

  val regs = RegNext(VecInit(Seq.fill(bits)(0.U(1.W))))
  
  when (io.load) {
    for (i <- 0 until bits) {
      regs(i) := io.init(i)
    } 
  }.otherwise {
    for (i <- 0 until bits - 1) {
      regs(i+1) := regs(i)
    }
  }
  
  io.out := regs.asUInt
}
